In recent years, electrical and computing systems that utilize microelectronic devices, such power integrated circuits (IC), have become increasingly complicated. In order to protect various components used in a wide variety of systems, such as automobiles and the like, self-testing features (i.e., built-in testing apparatuses or “testers”) are often provided which allow the microelectronic devices to be tested for appropriate shut off current levels.
In order to minimize costs, multiple devices are often tested simultaneously by the same tester, or testers. However, the maximum testing current that can be provided by typical tester is insufficient to fully test some modern devices. For example, some modern power ICs have channels capable of handling maximum peak currents of over 15 A, while most testers are not able to provide more than 10 A. Therefore, multiple testers are often connected in parallel to provide a sufficient amount of current for fully testing such devices.
However, the use of multiple testers defeats the goal of minimizing costs, as more testers are required within the system, which again increases testing costs. Additionally, high current operation considerably raises the temperature of the devices, which reduces the longevity and reliability of the devices.
Accordingly, it is desirable to provide a system and method for testing electronic devices with a reduced amount of current. Additionally, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.